Operating Systems and Kernels

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An Operating System (OS) acts as an interface between a computer user and hardware. It performs file management, memory management, process management, input/output handling, and controls peripheral devices such as disk drives and printers.

• Operating System: Software that enables applications to interact with a computer’s hardware.
• Kernel: Contains the operating system’s core components (essentially a lightweight core OS).

Instructions and Addressing Modes

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A program is a sequence of instructions supported by the Instruction Set Architecture (ISA) of a microprocessor. Instructions are fetched from memory and executed sequentially.

Instruction Cycle

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1. Fetch the instruction.
2. Decode the instruction.
3. Locate the operands.
4. Fetch operands from memory if needed.
5. Execute the operation in the processor register.
6. Store the results in the proper place.

Example: ADD AX, [100]

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(Where [xx] denotes memory contents at address xx)

• Before execution: Memory address 100 holds [23H], register AX holds [11H]
• After execution: Memory address 100 holds [23H], register AX holds [34H]

Addressing Modes & Registers (x86 / 8086)

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Addressing modes define the different ways a processor can access memory to locate data for manipulation.

8086 Architecture (16-bit Processor Basics)

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• AX (16-bit accumulator) = AL (Low byte) + AH (High byte)
• General Registers: AX, BX, CX, DX (and their respective high/low byte parts).
• Pointer Registers: SP (Stack Pointer), BP (Base Pointer).
• Index Registers: SI (Source Index), DI (Destination Index).
• Segment Registers: CS (Code Segment), DS (Data Segment), SS (Stack Segment), ES (Extra Segment).
• Instruction Pointer: IP.
• Flag Register: FR (indicates conditions/status).

Intel 32-bit / 64-bit Architecture Registers

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• RAX / EAX / AX / AH/AL: Extended register hierarchies.
• AX: Used for multiplication, division, and adjustments.
• BX: Holds offset addresses.
• CX: Holds loop/instruction counts.
• DX: Holds parts of multiplication results or pre-division data.
• BP: Points to memory locations for data transfer.
• DI / SI: Destination and source string data pointers.
• IP: Addresses the next instruction.
• SP: Addresses the top of the stack.
• FS / GS: Additional segment registers for specialized program data.

Instruction Basics & Real Mode

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Immediate Addressing & Rules

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An addressing mode tells the CPU how to locate the data it wants to manipulate (e.g., MOV DL, 44H moves the immediate value 44H into DL).

Important Rule: It is illegal to move an immediate number directly into a segment register.

• Incorrect: MOV DS, 2345H
• Correct: mov AX, 2341H followed by mov DS, AX

Real Mode & Segmentation

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• Real Mode: Operates on the first 1 megabyte of memory.
• Segments and Offsets: Uses a combination of segment and offset addresses in real mode to generate physical memory locations.

Real Mode Address Calculation (20-bit)

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• Segment Address: Defines the base starting address on a 64KB memory boundary.
• Offset: Selects any location within that 64KB block (size equals 2^16 bytes, since 2^6 * 2^10 = 64KB).
• Formula: Physical Address = (Segment Register * 10H) + Offset Register

Calculation Example:

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Given Segment Register = 1000H and Offset Register = F000H:

  10000H  (Segment shifted left by 4 bits / multiplied by 16)
+  F000H  (Offset)
---------
  1F000H  (20-bit real mode physical address)

Memory Efficiency

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• The 8086 typically utilizes 4 active segments simultaneously (CS, DS, SS, ES).
• Active Usable Memory: 4 * 64KB = 256KB accessible at any given time within the 1MB address space.
• Efficiency Ratio: 256KB / 1MB = 25.6%

80x86 Addressing Modes & I/O

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Endianness Note:

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• Little Endian: Least significant byte stored at the lower address, high byte at the higher address (e.g., if address [1b67] = 69H and [1b68] = 1BH, value loaded into AX is 1B69H).

  flowchart LR
  subgraph LE [Little Endian: x86 / Modern Architectures]
  le1["Memory [1B67H]69H (Low Byte)"] --> le2["Memory [1B68H]1BH (High Byte)"]
  end
  

• Big Endian: High byte at the lower address.

  flowchart LR
  subgraph BE [Big Endian: Network Protocols / TCP-IP]
  be1["Memory [1B67H]1BH (High Byte)"] --> be2["Memory [1B68H]69H (Low Byte)"]
  end
  

• Usage Context: The majority of modern architectures use Little Endian, whereas network protocols like TCP/IP use Big Endian (Network Byte Order).

1. Register Addressing Mode

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Data is stored directly in registers.

• Example: MOV AX, BX

• Operation: Given AX = 0000H and BX = 1B69H, the value 1B69H moves into AX

2. Immediate Addressing Mode

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The operand is specified directly in the instruction.

• Example: mov ax, 1b67

• Operation: Moves 1B67H directly into AX.

3. Direct Addressing Mode

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The instruction contains the memory offset directly. DS is the default segment.

• Example: mov ax, [1b67]

• Can also write back to memory: mov [1024], al.

4. Register-Indirect Addressing Mode

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The memory address is held inside a base or index register.

• Example: mov ax, [bx]

• Operation: If [bx] points to address containing 24H and [bx+1] contains 01H, 0124H is loaded into AX.

5. Based, Indexed, and Based-Index Addressing Modes

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Combines base registers (BX or BP), index registers (SI or DI), and optional displacements.

• Indexed Addressing: Uses SI or DI with an optional displacement (e.g., mov ax, [si + 1b66]).

• Based-Index Addressing: Combines base and index registers with optional signed displacements (e.g., MOV AX, [BX+SI-2H], or MOV AX, [bx-3] using SS:BP stack context).

6. Direct I/O Port Addressing Mode

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Accesses hardware data mapped directly to I/O devices or ports (such as a keyboard using a 16-bit port number like 09H).

• Example: IN al, 09
• Operation: Fetches data from port 09 and saves it into the AL register.

flowchart LR
    a["CPU"]
    b["Port 09H"]
    c["Data (12H)"]
    d["AL Register"]

    a -->|Read Port| b
    b --> c
    c -->|Save| d

7.Relative Addressing Mode

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Accesses I/O ports via register or dynamic references.

• Example: IN al, DX (or indirect mapping structures).

flowchart TD
    a["CPU"]
    b["Port Address (09H)"]
    c["Offset Value:23H"]
    d["Port Number (FFH)"]
    e["AL Register"]

    a --> b
    b --> c
    c --> d
    d -->|Save Data| e

8. Relative Addressing Mode

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Specified relative to the Instruction Pointer (IP) by an 8-bit signed displacement, commonly used for conditional jumps like JZ (Jump if Zero).

ADD AX, BX         ; (e.g., AX = 0001H, BX = FFFFH -> Result = 0000H, Zero Flag = 1)
JZ 000AH           ; offset from IP location
MOV AX, FFH        ; fallback instruction

Execution Flow:

• If the result is zero (Zero Flag = 1), execution jumps to target address relative to CS:IP. For instance, with CS = 2000H and IP = 1000H:
  • Physical Target = 2000H x 10H + 1000H + 0AH = 2100AH
• Otherwise, execution proceeds sequentially to 1002H to run MOV AX, FFH.

9. Implied Addressing Mode

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Instructions that operate directly without explicit operands.

• Instructions that operate directly without explicit operands.
• example: CLC - Clear Carry Flag

Segment Override

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In 8086 architecture, a segment override is a prefix used in an assembly instruction to temporarily change which default segment register the processor uses to access memory.

How Default Segments Work Normally

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By default, the CPU assigns specific segment registers to particular pointer registers:

• DS (Data Segment) is the default for general data references (like [BX], [SI], [DI], or direct numeric offsets).
• SS (Stack Segment) is the default for stack operations using BP or SP (e.g., [BP + 4]).
• CS (Code Segment) is used for instruction fetches (IP).

What Segment Override Does

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If you want an instruction to read or write from a different segment than the default one without changing the segment register globally, you apply a segment override prefix.

• Example: Normally, MOV AX, [BX] uses the DS register. If you want it to fetch data from the Extra Segment (ES) instead, you add an override prefix: MOV AX, ES:[BX]
• Common Use Case: When working with string operations or multi-segment data structures where data resides outside the active DS or SS block, the override prefix ensures the instruction computes the 20-bit physical address using your explicitly chosen segment register instead of the fallback default.

Stack Memory and Operations

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Data movement instructions like PUSH and POP transfer data to and from the stack.

sequenceDiagram
    participant Main as Main Program
    participant System

    Note over Main: Store all current information to stack memory
    Main->>System: Call a function
    
    System-->>Main: Return to program
    Note over Main: Restore all information from the stack memory

Stack Operations: PUSH and POP

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• PUSHA: Copies registers to the stack.

• POPA: Removes contents from the stack back into the registers.

Stack Segment

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• holds data temporarily
• Stores return addresses for procedures and interrupts.
• Operates on a LIFO (Last-In-First-Out) memory structure.

Flag Registers and Conditional Execution

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High-level programming languages rely on conditional structures (like if-then-else, switch, for, and while loops). In assembly, these are handled via conditional jumps:

1. Perform a calculation (e.g., ADD AX, BX).
2. Check the Flag Register to inspect the status of the result.
3. Jump if the condition is met (e.g., JZ 0AH).

The Flag Register (Program Status Register)

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Contains a combination of conditional and control flags:

• OF (Overflow Flag): Set if the result of a signed operation is too large to fit in the destination.
  • 16-bit Check: Set if there is a carry from bit 14 (d14) but no carry from bit 15 (d15).
  • 8-bit Check: Set if there is a carry from bit 6 (d6) but no carry from bit 7 (d7).
  • Example: For 8-bit signed values ranging from -128 to 127, adding 100 + 50 = 150 causes an overflow.
• DF (Direction Flag): Controls string processing direction.
  • Set (1) if accessing string data from high to low memory locations (e.g., bye).
  • Reset (0) if accessing string data from low to high memory locations (e.g., eyb).
• IF (Interrupt Flag): Controls whether external maskable interrupts are enabled.
• SF (Sign Flag): Set if the sign bit (d15) of the result is 1.
• ZF (Zero Flag): Set if the computation result equals zero.
• PF (Parity Flag): Set if the number of 1 bits in the least significant byte of the result is even.

Advanced I/O Operations (IN and OUT)

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The 16-bit I/O address space supports up to 64K devices.

• Immediate Port Access: IN al, 0001H (fetches data from port 0001H directly into AL).
• Register Indirect Port Access: IN ax, DX (fetches port address stored in DX, e.g., if DX = 00FEH, gets data from port 00FEH into AX).
• OUT operates inversely, writing computer register data out to an external peripheral device.

Processor Instructions: Arithmetic, Logic, Shifts, and Rotates

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Basic Arithmetic Instructions

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• ADD: Binary addition.
• SUB: Performs subtraction.
• INC: Adds one to a register or memory content.
• DEC: Subtracts one from a register or memory content.
• MUL / IMUL: Unsigned and signed multiplication.
• DIV / IDIV: Unsigned and signed integer division, producing both quotient and remainder.

Arithmetic Extensions & Comparisons

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• ADC (Add with Carry): Adds operands plus the current value of the carry flag.
• SBB (Subtract with Borrow): Subtracts operands along with the borrow/carry flag.
• CMP (Compare): Compares two values by performing a subtraction internally (e.g., CMP AL, 3 computes AL - 3), but does not store the result—it only updates the flag register based on the outcome.

Logic Instructions

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• AND: Logical multiplication (bitwise AND).

• OR: Logical sum (bitwise OR).

• XOR: Exclusive OR.

• NEG: Negate instruction (computes the 2’s complement of a number).

• NOT: Not instruction (computes the 1’s complement of a number).

Shift Instructions

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Shifts reposition bits within a number, split into logical and arithmetic categories:

• Logical Shifts:
  • SHL (Shift Left)
  • SHR (Shift Right)
• Arithmetic Shifts:
  • SAL (Shift Arithmetic Left)
  • SAR (Shift Arithmetic Right - preserves the sign bit, used to multiply or divide signed numbers by powers of two).

Rotate Instructions

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Rotates target bits either directly or through the carry flag:

• ROL / ROR: Rotate Left / Rotate Right.
• RCL / RCR: Rotate through Carry Left / Rotate through Carry Right.